1. Field of the Invention
The present invention relates generally to storage device controllers, and more particularly, to controlling read gate timing for hard disk controllers.
2. Background
Conventional computer systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and storage devices (for example, disk driver, tape drives) (referred to herein as “storage device”).
In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
A storage device is typically coupled to the host system via a controller that handles complex details of interfacing the storage device to the host system. The controller performs numerous functions, for example, converting digital to analog data signals, disk formatting, error checking and fixing, logical to physical address mapping and data buffering. Communications between the host system and the controller is usually provided using one of a variety of standard I/O bus interfaces.
Typically, when data is read from a storage device, a host system sends a read command to the controller, which stores the read command into the buffer memory. Data is read from the device and stored in the buffer memory. Buffer memory may be a Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (referred to as “DDR”).
Typically, a disk drive (or storage device, used interchangeably) includes one or more magnetic disks. Each disk (or platter) typically has a number of concentric rings or tracks (platter) on which data is stored. The tracks themselves may be divided into sectors, which are the smallest accessible data units. A positioning head above the appropriate track accesses a sector. An index pulse typically identifies the first sector of a track. The start of each sector is identified with a sector pulse. Typically, the disk drive waits until a desired sector rotates beneath the head before proceeding with a read or write operation. Data is accessed serially; one bit at a time and typically, each disk has its own read/write head.
To access data from a disk drive (or to write data), the host system must know where to read (or write data to) the data from the disk drive. A driver typically performs this task. Once the disk drive address is known, the address is translated to cylinder, head and sector, based on platter geometry and sent to the disk controller. Logic on the hard disk looks at the number of cylinders requested. Servo controller firmware instructs motor control hardware to move read/write heads to the appropriate track. When the head is in the correct position, it reads the data from the correct track.
Typically, a read and write head has a write core for writing data in a data region, and a read core for magnetically detecting the data written in the data region of a track and a servo pattern recorded on a servo region. A servo system detects the position of the head on a platter according to the phase of a servo pattern detected by the read core of the head. The servo system then moves the head to the target position.
A servo controller in the servo system communicates with a data recovery device. One such device is the “read channel device”. An example of such a product is “88C7500 Integrated Read channel” device sold by Marvell Semiconductor Inc ®. The read channel device is coupled to the controller and the disk drive.
A read gate (“RG”) signal is sent to the read channel device to control data read operations. The RG signal is asserted and de-asserted at a certain time, based on the code word encoding method used by the Read Channel device. In a conventional system, the RG signal is asserted/de-asserted on a specific code word boundary (for example, “mod 6” boundary i.e. at multiples of six symbols) of the write clock. However sector sizes continue to change and conventional systems, instead of precisely controlling the assertion/de-assertion of the RG signal to allow partial code word operations, sacrifice storage media utilization by padding the data stream with additional symbols of zero to reach a full code word boundary where RG is de-asserted.
Therefore, there is a need for a system and method for efficiently controlling the assertion/de-assertion of RG signals, which improves storage media utilization.